1. Technical Field
This disclosure relates to a system and method for testing a semiconductor device, and more particularly, to a system and method for testing a multi-port semiconductor device.
2. Description of the Related Art
In general, a semiconductor device test system includes a semiconductor device and a test apparatus. The function and operating speed of the semiconductor device are predetermined according to its purposes. The operating speed of the semiconductor device depends on the frequency of an external or internal clock signal. Since the semiconductor device should be capable of normal functions at a predetermined operating speed, the frequency of the clock signal significantly affects the performance of the semiconductor device.
Accordingly, the test apparatus of the semiconductor device test system should test not only the function of the semiconductor device but also the operating speed thereof. Thus, the test apparatus should apply test data to the semiconductor device with a clock signal corresponding to the predetermined frequency and test whether the semiconductor device performs normal functions. When the test apparatus applies test data corresponding to a clock signal with a frequency higher or lower than the predetermined frequency, the reliability of the test result is degraded.
FIG. 1 is a diagram of a conventional single-port semiconductor device test system. Although a typical semiconductor device test system is constructed such that a test apparatus 1 tests a plurality of semiconductor devices 2 at the same time, for brevity FIG. 1 illustrates a system in which the test apparatus 1 tests only a single semiconductor device 2.
Referring to FIG. 1, the test apparatus 1 includes a frequency generation unit 10, a test data generation unit 20, and a data determination unit 30. The test apparatus 1 further includes an output driver ODR and an input driver IDR.
The frequency generation unit 10 generates a frequency corresponding to the semiconductor device 2 to be tested. The frequency generation unit 10 includes a low-frequency generator 11, a frequency controller 12, and a reference frequency generator 13. The low-frequency generator 11 generates a stable low-frequency signal Lfreq. The low-frequency generator 11 may generate the low-frequency signal Lfreq using a low-frequency generation apparatus, such as a crystal oscillator. The frequency controller 12 outputs a frequency control signal Fcon, which is set by a user, to the reference frequency generator 13. Also, the reference frequency generator 13 converts the low-frequency signal Lfreq into a high-frequency reference frequency signal Pfreq in response to the frequency control signal Fcon. The low-frequency generation apparatus, such as the crystal oscillator, cannot generate a stable high-frequency signal. Also, the frequency generation unit 10 should be constructed to generate different frequencies according to a user's setting. Thus, the reference frequency generator 13 multiplies the frequency of the low-frequency signal Lfreq generated by the low-frequency generator 11 in response to the frequency control signal Fcon applied from the frequency controller 12, and generates the high-frequency reference frequency signal Pfreq for testing the semiconductor device 2.
The test data generation unit 20 includes an operation clock generator 21, a pattern data generator 22, a driver clock generator 23, and a driver controller 24. The operation clock generator 21 generates an operation clock signal Nclk corresponding to the operating speed of the semiconductor device 2 to be tested in response to the reference frequency signal Pfreq. The pattern data generator 22 outputs test data Tdata in response to the operation clock signal Nclk. Here, the test data Tdata is data that is preset to test the semiconductor device 2. The test apparatus 1 should store normal output data of the semiconductor device 2 with respect to the test data Tdata. In other words, the test apparatus 1 should store test expectation data that the semiconductor device 2 should output after the semiconductor device 2 receives the test data Tdata. Like the operation clock generator 21, the driver clock generator 23 generates a driver clock signal Dclk in response to the reference frequency signal Pfreq. The driver clock signal Dclk is a clock signal for controlling the operation timing of the output driver ODR of the test apparatus 1. The driver controller 24 outputs a driver control signal Dcon for controlling the output driver ODR in response to the driver clock signal Dclk. Although it is illustrated in FIG. 1 that the operation clock generator 21 and the driver clock generator 23 are separately provided, when the driver controller 24 is constructed to receive the operation clock signal Nclk from the operation clock generator 21 and control the output driver ODR, the driver clock generator 23 may be omitted.
The data determination unit 30 includes a strobe generator 31 and a logic determiner 32. The strobe generator 31 generates a strobe signal “str” in response to the reference frequency signal Pfreq. There are few cases where the semiconductor device 2 is independently used. That is, the semiconductor device 2 should receive data from and transmit data to an external device, such as another semiconductor device. For this, the semiconductor device 2 should receive input data from the external device and transmit output data to the external device at a specific point in time. When the semiconductor device 2 outputs the output data too fast or slowly, the external device cannot precisely receive the output data from the semiconductor device 2. Therefore, the semiconductor device 2 should output the output data to the external device at a specific point in time. The strobe signal “str” is a signal for determining if output test data Tout output from the semiconductor device 2 is precisely applied at a specific point in time. Thus, the strobe signal “str” allows the input driver IDR to receive the output test data Tout output from the semiconductor 2 only during an enabling period of the strobe signal “str.” The logic determiner 32 compares test result data Trst applied from the input driver IDR with the previously stored test expectation data corresponding to the test data Tdata and determines if the semiconductor device 2 is good or bad. The test expectation data is previously stored data that the semiconductor device 2 should output in response to the test data Tdata. When the test result data Trst is not equal to the test expectation data, it is determined that the corresponding semiconductor device 2 is bad.
The output driver ODR receives the test data Tdata under the control of the driver control signal Dcon and outputs input test data Tin to the semiconductor device 2. The input driver IDR receives the output test data Tout from the semiconductor device 2 in response to the strobe signal “str” and outputs the test result data Trst to the logic determiner 32.
The semiconductor device 2 receives the input data Tin and outputs the output data Tout via a port. The semiconductor device 2 performs a previously designed function in response to the input test data Tin and outputs the output test data Tout as the result of the performed function.
With technical developments, semiconductor devices are increasingly becoming high-integrated and multifunctional. However, the ongoing downscaling of various electronic appliances has led to a strong need for more high-integrated and multifunctional semiconductor devices. As a result, multi-port semiconductor devices are being developed and employed. A multi-port semiconductor device is a single semiconductor device including a plurality of input/output (I/O) ports. In this case, the multi-port semiconductor device may input and output different data via the respective ports with respect to the single semiconductor device. The single semiconductor device may include a plurality of function blocks corresponding to the respective ports so that the function blocks can perform respectively different operations. Alternatively, clock signals and data corresponding to different frequencies via the respective ports may be applied to the multi-port semiconductor device with respect to the single semiconductor device including a single function block.
FIG. 2 is a diagram of a conventional multi-port semiconductor device test system.
FIG. 2 illustrates a semiconductor device including four function blocks, which is an example of a multi-port semiconductor device.
When all the function blocks 3-1 to 3-4 of the multi-port semiconductor device 3 operate in response to the same operation clock signal, a test apparatus 1 of the multi-port semiconductor device 3 is similar to the test apparatus 1 of the single-port semiconductor device test system shown in FIG. 1. However, since the multi-port semiconductor device 3 is employed as a semiconductor device, a plurality of ports port1 to port4 of the semiconductor device 3 receive input test data Tin from the test apparatus 1 and transmit output test data Tout to the test apparatus 1. It is illustrated in FIG. 2 that each of the ports port1 to port4 receives the input test data Tin from a single output driver ODR and transmits the output test data Tout to a single input driver IDR. However, when the respective function blocks 3-1 to 3-4 receive different input test data Tin and transmit output test data Tout, the test apparatus 1 may include a plurality of input drivers IDR and a plurality of output drivers ODR corresponding respectively to the ports port1 to port4.
Since the test apparatus 1 shown in FIG. 2 is the same as the test apparatus 1 shown in FIG. 1, a description thereof will be omitted here. Assuming that the plurality of function blocks 3-1 to 3-4 operate at the same speed, the test apparatus 1 applies the input test data Tin to the function blocks 3-1 to 3-4 via the ports port1 to port4 in order to test the semiconductor device 3. The function blocks 3-1 to 3-4 of the semiconductor device 3 perform predetermined different operations in response to the input test data Tin and output respective output test data Tout to the test apparatus 1.
That is, when the function blocks 3-1 to 3-4 operate at the same speed, the test apparatus 1 applies the input test data Tin to the function blocks 3-1 to 3-4 at the same time and receives the output test data Tout from the function blocks 3-1 to 3-4 at the same time, thereby shortening the time required for testing the semiconductor device 3.
However, when the function blocks 3-1 to 3-4 of the semiconductor device 3 operate at different speeds, for example, when a first function block 3-1 operates at a speed of 100 MHz, a second function block 3-2 operates at a speed of 133 MHz, a third function block 3-3 operates at a speed of 150 MHz, and a fourth function block 3-4 operates at a speed of 200 MHz, the test apparatus 1 should transmit input test data Tin and receive output test data Tout at the operating speed of one of the function blocks 3-1 to 3-4. Therefore, a test operation must be performed several times corresponding to each of the function blocks 3-1 to 3-4. As a result, it is time consuming to test the semiconductor device 3. Furthermore, when the plurality of function blocks 3-1 to 3-4 of the semiconductor device 3 are interlocked to input and output data, the conventional test apparatus 1, which applies the input test data Tin to the semiconductor device 3 at one of the operating speeds of the function blocks 3-1 to 3-4 during a one-time test operation, is not capable of performing a reliable test. In a worst case scenario, the test apparatus 1 is completely unable to perform test operations.